library ieee;
use ieee.std_logic_1164.all;

package mis_componentes is

component mplex2x1 is
port(a,b,s:in std_logic;
	f:out std_logic);
end component;


component mplex4x1 is
port(a,b,c,d:in std_logic;
	s:in std_logic_vector(1 downto 0);
	f:out std_logic);
end component;

end mis_componentes;
